Center of Excellence in High Performance Computing (cxHPC)

General remarks

The efficient use of modern supercomputers is closely connected with an extensive and qualified user training and user support. Thus, the aim of the project cxHPC (formerly known as BAUWIHR) is to provide a center of excellence for scientific supercomputing at the Friedrich-Alexander University of Erlangen-Nürnberg.

cxHPC addresses the following tasks:

• HPC support:

  Programming, Debugging, Optimization of HPC codes. Provide test accounts to all major german supercomputer centers for testing and optimization

• HPC training:

  Organize HPC tutorials and HPC lectures for students and users

• HPC information:

  Present information about the latest development in HPC: new architectures, programming models, available resources, global trends,....

The project HQS@HPC is partially funded by KONWIHR (Competence Network for Technical, Scientific High Performance Computing in Bavaria). cxHPC offers its services to all scientists at the universities in northern bavaria as well as to all KONWIHR projects.

Contact

If you are interested in cxHPC do not hestitate to contact us:

• Project manager:

  Dr. Gerhard Wellein
  Regionales Rechenzentrum Erlangen
  Martensstr. 1, 91058 Erlangen
  +49 (0)9131 852 8737
  gerhard.wellein@rrze.fau.de

• Staff

  Dr. Georg Hager and Thomas Zeiser
  Regionales Rechenzentrum Erlangen
  Martensstr. 1, 91058 Erlangen
  +49 (0)9131 852 8973 or +49 (0)9131 852 8737
  georg.hager@rrze.fau.de
  thomas.zeiser@rrze.fau.de

Partners

We work closely with

• Lehrstuhl für Strömungsmechanik (Prof. Durst)
• Lehrstuhl für Informatik 10 (Systemsimulation, Prof. Rüde).
• Lehrstühle für theoretische Physik
  • Prof. Toepffer (2)
  • Prof. Lenz (3)
• Lehrstuhl für theoretische Chemie (Prof. Görling)
• LRZ (Dr. Matthias Brehm)
• HLRS (R. Rabenseifner)

Links of Interest

• HPC Services at Regionales Rechenzentrum Erlangen
• HPC Services at Leibniz Rechenzentrum München
• Projects related to cxHPC
• Slides of talks and other informational material

Talks

• Zentralinstitut für Angewandte Mathematik, KfA Jülich, Mai 2001. Härtetest für die Hitachi SR8000: Hybride Architektur und Performance von Anwenderprogrammen im Vergleich mit modernen MPP- und Vektorrechnern

• C&C Research Laboratories, NEC Europe, St. Augustin, Mai 2001. Pseudovectorization and hybrid programming on the Hitachi SR8000: A performance comparison with traditional MPP and vector systems

• CRAY Users Group SUMMIT2001, Indian Wells (USA), Mai 2001. Exact Diagonalization of Large Sparse Matrices: A Challenge for Modern Supercomputers

• National Energy Research Scientific Computing Center (NERSC), Berkley (USA), September 2001. Introduction to architecture and performance of Europeans first TeraFlops supercomputer: The Hitachi SR8000

• Lawrence Livermore National Laboratory (USA), September 2001. Introduction to architecture and performance of Europeans first TeraFlops supercomputer: The Hitachi SR8000

• ZKI AK Supercomputing, Konrad Zuse Institut Berlin (ZIB), Oktober 2001. Der Memory-Server am Regionalen Rechenzentrum Erlangen

• ZKI AK Supercomputing, TU Chemnitz, Oktober 2002. Benchmarks Itanium2

• Peridot Performance Workshop, Leibniz-Rechenzentrum München, May 2002. Strongly Implicit Procedure - SipBench

• Hochleistungsrechnen in Wissenschaft und Forschung, KONWIHR Kolloquium, FAU Erlangen-Nürnberg, Juli 2002. Center of Excellence for High Performance Computing in Erlangen

• International Conference on High Performance Computing for Computational Science - VECPAR2002, Porto (Portugal), Juni 2002. Fast sparse matrix-vector multiplication for TFlops computers

• IGC Herbstmeeting, RRZE, September 2002. Erste Erfahrungen mit Itanium- und Itanium2-Systemen

• First joint HLRB and KONWIHR workshop, Garching, Oktober 2002. Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture

• CCS3, Los Alamos National Laboratory (USA), November 2002. Architecture and Performance Characteristics of the Hitachi SR8000-F1 TFlops System at LRZ Munich

• Zentrum für Höchstleistungsrechnen Dresden, Universität Dresden, Januar 2003. Architektur und Performancecharakteristik moderner HPC Systeme

• Institut für Physik, Universität Greifswald, Januar 2003. Architektur und Performancecharakteristik moderner HPC Systeme

• ZKI AK Supercomputing, RWTH Aachen, April 2003. HPC-Cluster am RRZE und LRZ: Beschaffung und Leistungsbewertung (gemeinsam mit Dr. Brehm (LRZ)) Hybride Programmiermodelle für SMP-Cluster (gemeinsam mit Dr. Rabenseifner (HLRS))

• efi-Kolloquium, Georg-Simon-Ohm-Fachhochschule Nürnberg, April 2003. Die Welt der Supercomputer

• SGI 2003 Technical Users´ Conference, Mountain View (USA), Juni 2003. Application Performance of State-of-the-Art Processors: A Comparison

• LRZ-Tutorial, Juli 2003. Efficient Programming in Fortran, C and C++ - Selected Case Studies

Publications

• G. Wellein, G. Hager, A. Basermann and H. Fehske, CD CUG Summit 2001, Indian Wells, USA, April 2001. Exact Diagonalization of Large Sparse Matrices: A Challenge for Modern Supercomputers

• G. Wellein, G. Hager, A. Basermann and H. Fehske, in J.M.L.M. Palma et al. (Eds.): High Performance Computing for Computational Science - VECPAR2002, LNCS 2565, pp. 287-301. Springer-Verlag Berlin Heidelberg (2003) Fast sparse matrix-vector multiplication for TFlops computers

• G. Hager, F. Deserno and G. Wellein, in S. Wagner et al. (Eds.): High Performance Computing in Science and Engineering Munich 2002, pp. 425-442. Springer-Verlag Berlin Heidelberg (2003) Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture

• R. Rabenseifner and G. Wellein, The International Journal of High Performance Computing Applications 17, No. 1, Spring 2003, pp. 49-62 (2003). Communication and Optimization Aspects of Parallel Programming Models on Hybrid Architectures

• G. Hager, F. Brechtefeld, P. Lammers and G. Wellein, inSiDE Vol. 1 No. 1 Spring 2003, pp. 8-13 (2003). Processor Architecture and Application Performance in Modern Supercomputers

Workshops and Tutorials

• 05.12.-07.12.2000: Parallel Programming and Optimization Techniques for the Hitachi SR8000-F1, LRZ München. (Organisation und Durchführung gemeinsam mit LRZ München und Hitachi)

• 08.10.-11.10.2001: Programming and Optimization Techniques for Parallel Computers, RRZE. (Organisation und Durchführung gemeinsam mit LRZ München und Silicon Graphics)

• 09.09.-13.09.2002: Programming and Optimization Techniques for Parallel Computers, RRZE. (Organisation und Durchführung gemeinsam mit LRZ München und Silicon Graphics)

• 28.01.2003: Itanium2: Architektur, Programmier- und Optimierungsstrategien, RRZE (Organisation und Durchführung gemeinsam mit Intel)

• 01.04.2003: IBM Power4: Programmierung und Optimierung, RRZE (Organisation und Durchführung gemeinsam mit IBM)